1. Field of Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM).
2. Description of Related Art
As microprocessors become more powerful, the amount of software programs that can be simultaneously handled inside a computer increases exponentially. Consequently, the amount of memory necessary for storing data increases correspondingly, and hence high-efficiency storage capacitors are in great demand, too. As the level of integration of DRAM increases, DRAM cells are now constructed from just one transfer field effect transistor and a storage capacitor. FIG. 1 is an equivalent circuit diagram of a DRAM cell. A DRAM is normally constructed from an array of these cells. A binary bit is stored in the capacitor C of each cell. In general, when the capacitor C is free of charges, a logic state of "0" is defined.
On the other hand, when the capacitor C is fully charged, a logic state of "1" is defined. A capacitor C has an upper electrode (cell electrode) 100 and a lower electrode (storage electrode) 101 with a layer of dielectric 102 sandwiched between the two to provide the necessary dielectric constant. In addition, the capacitor C is coupled to a bit line (BL), and reading and writing to and from the DRAM memory is achieved by charging or discharging the capacitor C. Charging and discharging of the capacitor is carried out through the control of a transfer field effect transistor (TFET).
The source terminal of the transfer transistor is connected to the bit line BL, and the drain terminal of the transfer transistor is connected to the capacitor C. The transfer transistor is switched on or off through a selection signal coming from a word line WL, which is connected to the gate terminal of the transfer transistor. Hence, whether the capacitor C is connected to the bit line allowing for charging or discharging of the capacitor depends upon the selection signal passed to the gate terminal.
Functionally, the capacitor can be regarded as the heart of a DRAM device. When the quantities of electric charges stored in a capacitor are increased, data coming from the memory will be less affected by noise surrounding the communication system. In general, the charge storage capacity of a capacitor can be increased in several ways, including: 1. Choosing a material having a high dielectric constant to form the dielectric film layer. 2. Reducing the thickness of the dielectric film layer. 3. Increasing the surface area of a capacitor.
Nowadays, many materials with high dielectric constant are developed including tantalum pentoxide (Ta.sub.2 O.sub.5), Pb(Zr,Ti)O.sub.3 or PZT and (Ba,Sr)TiO.sub.3 or BST. To increase the surface area of a capacitor, a three-dimensional capacitor such as the so-called stacked type and trench type are now commonly used. For a 64 Mbit DRAM, for example, one method of further increasing the surface area of a capacitor is to extend the electrode and dielectric film layer horizontally and then stack the layers up to form a fin-type stacked capacitor. An alternative method is to allow the electrode and the dielectric film layer to extend vertically up to form a cylindrical-type stacked capacitor.
Description related to the formation of a fin-type capacitor can be found in an article by Ema et al. with the title "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" published in International Electron Devices Meeting, pp 592-595, December 1988, or U.S. Pat. No. 5,071,783, U.S. Pat. No. 5,126,810 and U.S. Pat. No. 5,206,787. Description related to the formation of a cylindrical-type capacitor can be found in another article by Wakamiya et al. with the title "Novel Stacked Capacitor Cell for 64Mb DRAM" published in Symposium on VLSI Technology Digest of Technical Papers, pp 69-70, 1989, or U.S. Pat. No. 5,077,688.
FIG. 2 is a cross-sectional view showing a DRAM having a conventional cylindrical capacitor. A DRAM is constructed above the surface of a substrate 200 within a specially defined active region that is surrounded by isolating insulator 201. The field effect transistor 202 of a DRAM includes a gate structure 203 and source/drain regions 204 and 205. The gate structure 203 includes a cap layer 209 on top and sidewall spacers 210 on each side, while the bit line 222 is electrically coupled with the source/drain region 204 of the transistor.
The bit line 222 is formed by first forming a dielectric layer 212 over the substrate 200, and then forming a self-aligned contact opening 214 using conventional photolithographic and etching processes. Finally, a conductive layer is deposited, filling the contact opening 214, and followed by patterning the conductive layer to form the bit line 222. The storage electrode 250 of the capacitor 255 is formed by first depositing a silicon oxide layer 226 over the substrate 200, and then depositing a borophosphosilicate glass (BPSG) layer 228 to form a planar surface. Next, the BPSG layer 228 and the silicon oxide layer 226 are patterned to form the contact opening 234.
Thereafter, a polysilicon layer 250a and another borophosphosilicate layer (not shown in the FIG. 2 are formed, patterned and then doped. Thereafter, another doped polysilicon layer is formed over the substrate 200 and then etched back to form doped polysilicon sidewall spacers 250b. Next, the borophosphosilicate glass layer is removed to expose the doped polysilicon layers 250a and 250b. The exposed polysilicon layers 242a and 242b together form the storage electrode 250. Finally, a dielectric thin film 252 and a conductive layer 254 are formed sequentially over the substrate 200 to complete the formation of a DRAM capacitor 255.
When the borophosphosilicate glass layer 228 and the silicon oxide layer 226 are etched to form the contact opening 234 of the cylindrical capacitor, the position of the opening 234 can be displaced due to the inherent difficulties in aligning a narrow width using conventional photolithographic techniques. In some cases, if sideward displacement is large, etching may result in actual damage to the bit line 222. When the bit line 222 is damaged, subsequently deposited doped polysilicon inside the contact opening 234 may short-circuit with the bit line 222.
Furthermore, although the cylindrical-shaped storage electrode 250 of the capacitor 255 is able to increase the capacitance of the memory device a little, the increase in capacitance may be less than the degree of shrinkage in device area due to a higher level of integration.
In light of the foregoing, there is a need to improve the method of fabricating dynamic random access memory and its capacitor.